1. Field of the Invention
The present invention relates to a digital data transmission technique.
2. Description of the Related Art
In conventional digital wired communication, a binary transmission method using time division multiplexing (TDM) has been the mainstream. In this case, high-capacity transmission has been realized by parallel transmission or high-rate transmission. In order to overcome the physical limitations on parallel transmission, serial transmission, which is high-speed transmission, is performed at a data rate of several Gbps to 10 Gbps or more using a high-speed interface (I/F) circuit. However, the data rate acceleration also has a limit, leading to a problem of BER (Bit Error Rate) degradation due to high-frequency loss or reflection in the transmission line.
On the other hand, with the digital wireless communication method, multi-bit information carried by a carrier signal is transmitted and received. That is to say, the data rate is not directly limited by the carrier frequency. For example, in QAM (Quadrature Amplitude Modification), which is the standard quadrature modulation/demodulation method, 4-value transmission is provided using a single channel. Furthermore, 64-QAM provides 64-value transmission using a single carrier. That is to say, such a multi-modulation method raises the transmission capacity without raising the carrier frequency.
Also, such a modulation/demodulation method can also be applied to wired communication in the same way as with wireless communication. Such a modulation/demodulation method has begun to be applied as the PAM (Pulse Amplitude Modulation) method, QPSK (Quadrature Phase Shift Keying) method, or DQPSK (Differential QPSK) method. In particular, in the field of optical communication, from the cost perspective, it is important to increase the information carried by a single optical fiber. This has shifted the technology trend from binary TDM to transmission using such digital modulation.
In the near future, such a digital multi-level modulation/demodulation method has the potential to be applied to a wired interface between devices such as memory, SoC (System On a Chip), etc. However, at the present time, there is no known multi-channel test apparatus which is capable of testing such devices for mass production.
Mixed test apparatuses and RF (Radio Frequency) test modules are known, which test a conventional wireless communication device. However, typical conventional wireless communication devices have a single or several I/O (input/output) communication ports (I/O ports), and thus conventional test apparatuses and test modules include only several communication ports. Accordingly, it is difficult to employ such a test apparatus or a test module to test a device, such as memory, having from tens of to a hundred or more I/O ports.
Furthermore, with the conventional test apparatuses for RF signals, signals output from a DUT (Device Under Test) are A/D (analog/digital) converted, and large amounts of data thus obtained are subjected to signal processing (including software processing) so as to perform expected value judgment. This leads to a long testing time.
Furthermore, digital pins included in conventional test apparatuses are provided, basically assuming that a binary signal (in some cases, a three-value signal further including the high-impedance state (Hi-Z)) is to be tested. That is to say, conventional test apparatuses including such digital pins have no demodulation function for a digitally modulated signal.
In a case in which all the I/O ports of a device such as memory, MPU (Micro Processing Unit), etc., are configured using the digital multi-level modulation method, such a single device has from tens of to a hundred or more I/O ports. Accordingly, there is a need to test such hundreds of I/O ports at the same time. That is to say, there is a need to provide a test apparatus having thousands of input/output channels for digitally modulated/demodulated signals. Furthermore, real-time testing at the hardware level is required in all steps due to the CPU resource limits of the test apparatus.